Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
In an attempt to further increase circuit density, three-dimensional (3D) ICs have been investigated. In a typical formation process of a 3D IC, at least two dies or wafers are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, one attempt involved bonding two dies or wafers on top of each other. The stacked dies were then bonded to a packaging substrate and wire bonds or solder bumps electrically coupled contact pads on each die to contact pads on the packaging substrate.
Another 3D package utilized package-on-package (PoP) or interposer techniques for stacking dies to reduce form factor. PoP typically includes one packaged die placed over another packaged die, wherein the dies are electrically coupled by solder bumps. The bottom die is then electrically coupled to a packaging substrate. PoP packages, however, are difficult to decrease the form factor. Additionally, current techniques utilizing an interposer as the packaging substrate are limited by its still 2D-like (sometimes referred to as 2.5D) features that make it difficult to minimize the x-y dimension.